ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 39

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7.3.6
7.3.7
7.4
7.4.1
8008H–AVR–04/11
Register Description
Port Pins
On-chip Debug System
SMCR – Sleep Mode Control Register
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to
Input Disable Register 0” on page 180
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the
main clock source is enabled and hence always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
The Sleep Mode Control Register contains control bits for power management.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 2:1 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select between the available sleep modes as shown in
Table 7-2.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
Bit
0x33 (0x53)
Read/Write
Initial Value
SM1
0
0
1
1
Sleep Mode Select
CC
I/O
R
7
–
0
“DIDR1 – Digital Input Disable Register 1” on page 163
/2 on an input pin can cause significant current even in active mode. Digital
) and the ADC clock (clk
SM0
0
1
0
1
R
6
–
0
“Digital Input Enable and Sleep Modes” on page 65
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Reserved
CC
/2, the input buffer will use excessive power.
R
5
–
0
for details.
ADC
R
4
–
0
) are stopped, the input buffers of the device will
R
3
–
0
SM1
R/W
2
0
Table
SM0
R/W
1
0
7-2.
ATtiny48/88
and
“DIDR0 – Digital
R/W
SE
0
0
for details on
SMCR
39