ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 201

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ATtiny48

Manufacturer Part Number
ATtiny48
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny48

Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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8008H–AVR–04/11
Figure 21-7. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction.
The Chip Erase operation turns the content of every memory location in both the Program and
EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
• Minimum low period of serial clock:
• Minimum high period of serial clock:
– When f
– When f
– When f
– When f
1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the
2. V
CLKI pin.
CC
ck
ck
ck
ck
- 0.3V <
< 12MHz: > 2 CPU clock cycles
>= 12MHz: 3 CPU clock cycles
< 12MHz: > 2 CPU clock cycles
>= 12MHz: 3 CPU clock cycles
MOSI
MISO
SCK
AV
CC
< V
CC
+ 0.3V, however, AV
CLKI
RESET
GND
(1)
CC
should always be within 1.8 – 5.5V
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
ATtiny48/88
(2)
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