ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 203

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.3.3
Table 21-8.
8008H–AVR–04/11
Instruction/Operation
Programming Enable
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
Load Instructions
Load Extended Address byte
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
Read Signature Byte
Read Fuse bits
Read Fuse High bits
Read Fuse Extended Bits
Read Calibration Byte
Write Instructions
Programming Instruction set
Serial Programming Instruction Set (Hexadecimal values)
Table 21-8 on page 203
(1)
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed): Set RESET to “1”. Turn V
– B: The EEPROM array is programmed one page at a time. The Memory page is
content at the selected address at serial output MISO.
operation.
Table
programmed.
loaded one byte at a time by supplying the 6 LSB of the address and data together
with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is
stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of
the address. When using EEPROM page access only byte locations loaded with the
Load EEPROM Memory Page instruction is altered. The remaining locations remain
unchanged. If polling (RDY/BSY) is not used, the used must wait at least t
before issuing the next byte (See
the data file(s) need to be programmed.
21-9). In a chip erased device, no 0xFFs in the data file(s) need to be
Byte 1
and
$AC
$AC
$4D
$C1
$A0
$F0
$48
$40
$28
$20
$58
$30
$50
$58
$50
$38
Figure 21-8 on page 204
Table
0000 00aa
adr MSB
adr MSB
Byte 2
$53
$80
$00
$00
$00
$00
$00
$00
$00
$00
$08
$08
$00
Instruction Format
21-9). In a chip erased device, no 0xFF in
describes the Instruction set.
Extended adr
0000 000aa
0000 000aa
aaaa aaaa
adr LSB
adr LSB
adr LSB
adr LSB
Byte 3
CC
$00
$00
$00
$00
$00
$00
$00
$00
power off.
ATtiny48/88
high data byte out
low data byte out
high data byte in
low data byte in
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
WD_EEPROM
Byte4
$00
$00
$00
203