ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 27

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ATtiny48

Manufacturer Part Number
ATtiny48
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny48

Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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5.4.4
5.4.5
5.4.6
8008H–AVR–04/11
GPIOR2 – General Purpose I/O Register 2
GPIOR1 – General Purpose I/O Register 1
GPIOR0 – General Purpose I/O Register 0
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,
the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
This is the read strobe of the EEPROM. When the target address has been set up in the EEAR,
the EERE bit must be written to one to trigger the EEPROM read operation.
EEPROM read access takes one instruction, and the requested data is available immediately.
When the EEPROM is read, the CPU is halted for four cycles before the next instruction is
executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in
progress, it not possible to read the EEPROM, or to change the address register (EEAR).
This register may be used freely for storing any kind of data.
This register may be used freely for storing any kind of data.
This register may be used freely for storing any kind of data.
Bit
0x2B (0x4B)
Read/Write
Initial Value
Bit
0x2A (0x4A)
Read/Write
Initial Value
Bit
0x1E (0x3E)
Read/Write
Initial Value
MSB
MSB
MSB
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
ATtiny48/88
LSB
R/W
LSB
R/W
LSB
R/W
0
0
0
0
0
0
GPIOR2
GPIOR1
GPIOR0
27

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