ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 18

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.2
5.2.1
5.2.2
18
Data Memory (SRAM) and Register Files
ATtiny48/88
General Purpose Register File
I/O Register File
Table 5-2
memory areas are volatile, i.e. they do not retain information when power is removed.
Table 5-2.
Note:
The 512/768 memory locations include the general purpose register file, I/O register file,
extended I/O register file, and the internal data memory.
For compatibility with future devices, reserved bits should be written to zero, if accessed.
Reserved I/O memory addresses should never be written.
The first
described in detail in
Following the general purpose register file, the next
Registers in this area are used mainly for communicating with I/O and peripheral units of the
device. Data can be transferred between I/O space and the general purpose register file using
instructions such as IN, OUT, LD, ST, and derivatives.
All I/O registers in this area can be accessed with the instructions IN and OUT. These I/O spe-
cific instructions address the first location in the I/O register area as 0x00 and the last as 0x3F.
The low 32 registers (address range 0x00...0x1F) are accessible by some bit-specific instruc-
tions. In these registers, bits are easily set and cleared using SBI and CBI, while bit-conditional
branches are readily constructed using instructions SBIC, SBIS, SBRC, and SBRS.
Registers in this area may also be accessed with instructions LD/LDD/LDI/LDS and
ST/STD/STS. These instructions treat the entire volatile memory as one data space and, there-
fore, address I/O registers starting at 0x20.
See
Device
ATtiny48
ATtiny88
“Instruction Set Summary” on page
1. Also known as data address. This mode of addressing covers the entire data memory and reg-
2. Also known as direct I/O address. This mode of addressing covers part of the register area,
32
shows how the data memory and register files of ATtiny48/88 are organized. These
ister area. The address is contained in a 16-bit area of two-word instructions.
only. It is used by instructions where the address is embedded in the instruction word.
locations are reserved for the general purpose register file. These registers are
Layout of Data Memory and Register Area.
Memory Area
General purpose register file
I/O register file
Extended I/O register file
Data SRAM
General purpose register file
I/O register file
Extended I/O register file
Data SRAM
“General Purpose Register File” on page
281.
Size
32B
64B
160B
256B
32B
64B
160B
512B
64
locations are reserved for I/O registers.
Long Address
0x0000 – 0x001F
0x0020 – 0x005F
0x0060 – 0x00FF
0x0100 – 0x01FF
0x0000 – 0x001F
0x0020 – 0x005F
0x0060 – 0x00FF
0x0100 – 0x02FF
10.
(1)
Short Address
n/a
0x00 – 0x3F
n/a
n/a
n/a
0x00 – 0x3F
n/a
n/a
8008H–AVR–04/11
(2)