ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 36

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7. Power Management and Sleep Modes
7.1
7.1.1
36
Sleep Modes
ATtiny48/88
Idle Mode
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during
the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
See
Figure 6-1 on page 28
tion. The figure is helpful in selecting an appropriate sleep mode.
sleep modes, their wake up sources and the BOD disable ability.
Table 7-1.
Notes:
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM1, and SM0 bits in the SMCR Register select which sleep
mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction.
See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for
some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See
“External Interrupts” on page 53
When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, Analog Comparator, ADC, 2-wire Serial Interface,
Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode
basically halts clk
Sleep Mode
Idle
ADC Noise Reduction
Power-down
“Software BOD Disable” on page 37
Table 7-2 on page 39
1. For INT1 and INT0, only level interrupt
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
CPU
and clk
presents the different clock systems in the ATtiny48/88, and their distribu-
Active Clock Domain
for a summary.
FLASH
for details.
, while allowing the other clocks to run.
X
for more details.
X
X
Oscillator
X
X
X
X
X
(1)
(1)
Table 7-1
X
X
X
Wake-up Source
X
X
shows the different
X
X
8008H–AVR–04/11
X
X
X
X