ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 31

• Manufacturer Part Number: ATmega1281R231
• Manufacturer: Atmel Corporation

Specifications of ATmega1281R231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

2549N–AVR–05/11
Figure 9-3.
Note:
Figure 9-4.
Note:
System Clock (CLK
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction
accesses the RAM (internal or external).
SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal
or external).
External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
DA7:0
A15:8
CPU
ALE
WR
RD
DA7:0
A15:8
CPU
ALE
)
WR
RD
Prev. addr.
Prev. data
Prev. data
Prev. data
)
Prev. addr.
Prev. data
Prev. data
Prev. data
T1
ATmega640/1280/1281/2560/2561
T1
Address
Address
Address
T2
Address
Address
Address
XX
T2
XX
XXXXX
Address
T3
Data
Data
Data
Address
T3
Data
Data
Data
T4
XXXXXXXX
T4
T5
(1)
(1)
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