ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 290

• Manufacturer Part Number: ATmega1281R231
• Manufacturer: Atmel Corporation

Specifications of ATmega1281R231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

26.8.2
2549N–AVR–05/11
ADCSRB – ADC Control and Status Register B
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see
page
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
See
in effect until this conversion is complete (ADIF in ADCSRA is set).
• Bit 3 – MUX5: Analog Channel and Gain Selection Bit
This bit is used together with MUX4:0 in ADMUX to select which combination in of analog inputs
are connected to the ADC. See
the change will not go in effect until this conversion is complete.
This bit is not valid for ATmega1281/2561.
Table 26-4.
Bit
(0x7B)
Read/Write
Initial Value
000000
000001
000010
000011
000100
000101
000110
000111
MUX5:0
Table 26-4
294.
Input Channel Selections
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
Single Ended
for details. If these bits are changed during a conversion, the change will not go
R
7
–
0
Input
ACME
R/W
6
0
Table 26-4
ATmega640/1280/1281/2560/2561
Positive Differential
R
5
–
0
Input
for details. If this bit is changed during a conversion,
R
4
–
0
“ADCL and ADCH – The ADC Data Register” on
MUX5
R/W
3
0
ADTS2
Negative Differential
R/W
N/A
2
0
Input
ADTS1
R/W
1
0
ADTS0
R/W
0
0
ADCSRB
Gain
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