ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 112

• Manufacturer Part Number: ATmega1281R231
• Manufacturer: Atmel Corporation

Specifications of ATmega1281R231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

15. External Interrupts
15.1
2549N–AVR–05/11
Pin Change Interrupt Timing
The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23:0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23:0 pins are configured as
outputs. This feature provides a way of generating a software interrupt.
The Pin change interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin change
interrupt PCI1 if any enabled PCINT15:8 toggles and Pin change interrupts PCI0 will trigger if
any enabled PCINT7:0 pin toggles. PCMSK2, PCMSK1 and PCMSK0 Registers control which
pins contribute to the pin change interrupts. Pin change interrupts on PCINT23 :0 are detected
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0)
and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered,
the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising
edge interrupts on INT7:4 requires the presence of an I/O clock, described in
page
This implies that these interrupts can be used for waking the part also from sleep modes other
than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
An example of timing of a pin change interrupt is shown in
“System Clock and Clock Options” on page
40. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously.
ATmega640/1280/1281/2560/2561
40.
Figure 15-1 on page
113.
“Overview” on
112