ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 148

• Manufacturer Part Number: ATmega1281R231
• Manufacturer: Atmel Corporation

Specifications of ATmega1281R231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

17.9
Table 17-2.
2549N–AVR–05/11
Mode
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Modes of Operation
WGMn3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Waveform Generation Mode Bit Description
WGMn2
(CTCn)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
non-PWM modes refer to
page
page
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOCnx strobe bits.
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Out-
put mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare
match.
Note:
For detailed timing information refer to
159, and for phase correct and phase and frequency correct PWM refer to
160.
(PWMn1)
WGMn1
See “Compare Match Output Unit” on page 147.
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions.
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
However, the functionality and location of these bits are compatible with previous versions of
the timer.
(PWMn0)
WGMn0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 17-3 on page
PWM, Phase and Frequency
PWM, Phase Correct, 10-bit
PWM,Phase and Frequency
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
(1)
ATmega640/1280/1281/2560/2561
PWM, Phase Correct
PWM, Phase Correct
Mode of Operation
Fast PWM, 10-bit
Fast PWM, 8-bit
Fast PWM, 9-bit
Timer/Counter
(Reserved)
Fast PWM
Fast PWM
“Timer/Counter Timing Diagrams” on page
Normal
Correct
Correct
CTC
CTC
159. For fast PWM mode refer to
0xFFFF
OCRnA
OCRnA
0x00FF
0x01FF
0x03FF
0x00FF
0x01FF
0x03FF
OCRnA
OCRnA
ICRn
ICRn
ICRn
ICRn
TOP
–
Update of
OCRn
Immediate
Immediate
Immediate
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
TOP
TOP
TOP
TOP
TOP
–
x
at
Table 17-4 on
Table 17-5 on
156.
TOVn Flag
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
Set on
MAX
MAX
MAX
TOP
TOP
TOP
TOP
TOP
–
148