ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 107
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ATmega1281R231
Manufacturer Part Number
ATmega1281R231
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1281R231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
54
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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14.2
2549N–AVR–05/11
Reset and Interrupt Vector placement
Table 14-2
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt
Vectors are not used, and regular program code can be placed at these locations. This is also
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
Table 14-2.
Note:
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega640/1280/1281/2560/2561 is:
Address
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0X0018
0x001A
0x001C
0x001E
0x0020
0x0022
0x0024
0x0026
0x0028
0x002A
0x002C
0x002E
0x0030
0x0032
0x0034
0x0036
0x0038
0x003A
0x003C
0x003E
BOOTRST
1
1
0
0
1. The Boot Reset Address is shown in
332. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
Labels
shows Reset and Interrupt Vectors placement for the various combinations of
Reset and Interrupt Vectors Placement
IVSEL
0
1
0
1
Code
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
Boot Reset Address
Boot Reset Address
Reset Address
RESET
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
PCINT0
PCINT1
PCINT2
WDT
TIM2_COMPA
TIM2_COMPB
TIM2_OVF
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_COMPC
TIM1_OVF
TIM0_COMPA
TIM0_COMPB
TIM0_OVF
SPI_STC
USART0_RXC
USART0_UDRE
USART0_TXC
ANA_COMP
ADC
EE_RDY
TIM3_CAPT
ATmega640/1280/1281/2560/2561
0x0000
0x0000
Table 29-7 on page 328
Comments
; Reset Handler
; IRQ0 Handler
; IRQ1 Handler
; IRQ2 Handler
; IRQ3 Handler
; IRQ4 Handler
; IRQ5 Handler
; IRQ6 Handler
; IRQ7 Handler
; PCINT0 Handler
; PCINT1 Handler
; PCINT2 Handler
; Watchdog Timeout Handler
; Timer2 CompareA Handler
; Timer2 CompareB Handler
; Timer2 Overflow Handler
; Timer1 Capture Handler
; Timer1 CompareA Handler
; Timer1 CompareB Handler
; Timer1 CompareC Handler
; Timer1 Overflow Handler
; Timer0 CompareA Handler
; Timer0 CompareB Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; USART0 RX Complete Handler
; USART0,UDR Empty Handler
; USART0 TX Complete Handler
; Analog Comparator Handler
; ADC Conversion Complete Handler
; EEPROM Ready Handler
; Timer3 Capture Handler
Interrupt Vectors Start Address
(1)
Boot Reset Address + 0x0002
Boot Reset Address + 0x0002
0x0002
0x0002
through
Table 29-15 on page
107
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