AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 395

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 22-4.
32059L–AVR32–01/2012
0x032C
0x033C
0x034C
0x035C
0x036C
0x040C
0x0324
0x0328
0x0330
0x0334
0x0338
0x0340
0x0344
0x0348
0x0350
0x0354
0x0358
0x0360
0x0364
0x0368
0x0400
0x0404
0x0408
0x0410
Offset
USBB Register Memory Map
Device DMA Channel 2 HSB Address Register
Device DMA Channel 3 HSB Address Register
Device DMA Channel 4 HSB Address Register
Device DMA Channel 5 HSB Address Register
Device DMA Channel 6 HSB Address Register
Device DMA Channel 2 Control Register
Device DMA Channel 3 Control Register
Device DMA Channel 4 Control Register
Device DMA Channel 5 Control Register
Device DMA Channel 6 Control Register
Device DMA Channel 2 Status Register
Device DMA Channel 3 Next Descriptor
Device DMA Channel 3 Status Register
Device DMA Channel 4 Next Descriptor
Device DMA Channel 4 Status Register
Device DMA Channel 5 Next Descriptor
Device DMA Channel 5 Status Register
Device DMA Channel 6 Next Descriptor
Device DMA Channel 6 Status Register
Host Global Interrupt Enable Register
Host Global Interrupt Clear Register
Host Global Interrupt Set Register
Host General Control Register
Host Global Interrupt Register
Address Register
Address Register
Address Register
Address Register
Register
NEXTDESC
NEXTDESC
NEXTDESC
NEXTDESC
UHINTCLR
CONTROL
UHINTSET
CONTROL
CONTROL
CONTROL
CONTROL
UDDMA2
UDDMA2
UDDMA2
UDDMA3
UDDMA3
UDDMA3
UDDMA3
UDDMA4
UDDMA4
UDDMA4
UDDMA4
UDDMA5
UDDMA5
UDDMA5
UDDMA5
UDDMA6
UDDMA6
UDDMA6
UDDMA6
STATUS
STATUS
STATUS
STATUS
STATUS
UHINTE
UHCON
UHINT
ADDR
ADDR
ADDR
ADDR
ADDR
Name
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-Only
Read-Only
Write-Only
Write-Only
Access
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
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