AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 251

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.14.5
Name:
Access:
Offset:
Reset Value: 0x00000000
CWGR is only used in Master mode.
• CKDIV: Clock Divider
• CHDIV: Clock High Divider
• CLDIV: Clock Low Divider
32059L–AVR32–01/2012
T
T
low
high
31
23
15
–
7
The CKDIV is used to increase both SCL high and low periods.
The SCL high period is defined as follows:
The SCL low period is defined as follows:
=
=
Clock Waveform Generator Register
(
(
(
CLDIV
(
CHDIV
CWGR
Read-write
0x10
×
×
2
30
22
14
CKDIV
2
–
6
CKDIV
)
+
)
+
4 )
4 )
×
×
T
CLK_TWI
T
CLK_TWI
29
21
13
–
5
28
20
12
–
4
CHDIV
CLDIV
27
19
11
–
3
26
18
10
–
2
CKDIV
25
17
–
9
1
24
16
–
8
0
251