AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 381

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.7.3.3
22.7.3.4
22.7.3.5
22.7.3.6
32059L–AVR32–01/2012
Device detection
USB reset
Pipe reset
Pipe activation
sumption. The USB pad should be in the Idle state. Once a device is connected, the macro
enters the Ready state, what does not require the USB clock to be activated.
The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when
the host mode does not generate the “Start of Frame (SOF)”. In this state, the USB consumption
is minimal. The host mode exits the Suspend state when starting to generate the SOF over the
USB line.
A device is detected by the USBB host mode when D+ or D- is no longer tied low, i.e., when the
device D+ or D- pull-up resistor is connected. To enable this detection, the host controller has to
provide the VBus power supply to the device by setting the VBUSRQ bit (by writing a one to the
VBUSRQS bit).
The device disconnection is detected by the host controller when both D+ and D- are pulled
down.
The USBB sends a USB bus reset when the user write a one to the Send USB Reset bit in the
Host General Control register (UHCON.RESET). The USB Reset Sent Interrupt bit in the Host
Global Interrupt register (UHINT.RSTI) is set when the USB reset has been sent. In this case, all
the pipes are disabled and de-allocated.
If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable (SOFE) bit
in UHCON is zero), the USBB automatically switches it to the “Resume” state, the Host Wake-
Up Interrupt (HWUPI) bit in UHINT is set and the SOFE bit is set in order to generate SOFs
immediately after the USB reset.
A pipe can be reset at any time by writing a one to the Pipe n Reset (PRSTn) bit in the UPRST
register. This is recommended before using a pipe upon hardware reset or when a USB bus
reset has been sent. This resets:
The pipe configuration remains active and the pipe is still enabled.
The pipe reset may be associated with a clear of the data toggle sequence. This can be
achieved by setting the Reset Data Toggle bit in the Pipe n Control register (UPCONn.RSTDT)
(by writing a one to the Reset Data Toggle Set bit in the Pipe n Control Set register
(UPCONnSET.RSTDTS)).
In the end, the user has to write a zero to the PRSTn bit to complete the reset operation and to
start using the FIFO.
The pipe is maintained inactive and reset (see
disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset.
• The internal state machine of this pipe
• The receive and transmit bank FIFO counters
• All the registers of this pipe (UPCFGn, UPSTAn, UPCONn), except its configuration (ALLOC,
PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ in UPCFGn) and its Data Toggle
Sequence field in the Pipe n Status register (UPSTAn.DTSEQ).
Section 22.7.3.5
for more details) as long as it is
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