AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 318

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 21-31. T=0 Protocol with Parity Error
21.6.5.3
21.6.5.4
21.6.5.5
21.6.5.6
21.6.5.7
21.6.6
32059L–AVR32–01/2012
Baud Rate
Clock
I/O
IrDA Mode
Protocol T=1
Receive NACK Inhibit
Transmit Character Repetition
Receive Error Counter
Disable Successive Receive NACK
Start
Bit
D0
In T=1 protocol, the character resembles an asynchronous format with only one stop bit. The
parity is generated when transmitting and checked when receiving. Parity errors set PARE.
The USART receiver keeps count of up to 255 errors in the Number Of Errors field in the Num-
ber of Error Register (NER.NB_ERRORS). Reading NER automatically clears NB_ERRORS.
The USART can be configured to ignore parity errors by writing a one to the Inhibit Non
Acknowledge bit (MR.INACK). Erroneous characters will be treated as if they were ok, not gen-
erating a NACK, loaded to RHR, and raising RXRDY.
The USART can be configured to automatically re-send a character if it receives a NACK. Writ-
ing a value other than zero to MR.MAX_ITERATION will enable and determine the number of
consecutive re-transmissions. If the number of unsuccessful re-transmissions equal
MAX_ITERATION, the iteration bit (CSR.ITER) is set. Writing a one to the Reset Iteration bit
(CR.RSTIT) will clear ITER.
The receiver can limit the number of consecutive NACK’s to the value in MAX_ITERATION. This
is enabled by writing a one to the Disable Successive NACK bit (MR.DSNACK). If the number of
NACK’s is about to surpass MAX_ITERATION, the character will instead be accepted as valid
and ITER is set.
The USART features an IrDA mode, supporting asynchronous, half-duplex, point-to-point wire-
less communication. It embeds the modulator and demodulator, allowing for a glueless
connection to the infrared transceivers, as shown in
enables this mode, and activates the IrDA specification v1.1 compliant modem. Data transfer
speeds ranging from 2.4Kbit/s to 115.2Kbit/s are supported and the character format is fixed to
one start bit, eight data bits, and one stop bit.
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Figure
Time 1
Guard
Error
21-32. Writing 0x8 to MR.MODE
Time 2
Guard
Start
Bit
Repetition
D0
D1
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