AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 175

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.5.3
17.5.4
32059L–AVR32–01/2012
Interrupts
Interrupt Timings
The GPIO can be configured to generate an interrupt when it detects an input change on an I/O
line. The module can be configured to signal an interrupt whenever a pin changes value or only
to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the
corresponding bit in the Interrupt Enable Register (IER). The interrupt mode is set by writing to
the Interrupt Mode Register 0 (IMR0) and the Interrupt Mode Register 1(IMR1). Interrupts can be
enabled on a pin, regardless of the configuration of the I/O line, i.e. whether it is controlled by the
GPIO or assigned to a peripheral function.
In every port there are four interrupt lines connected to the interrupt controller. Groups of eight
interrupts in the port are ORed together to form an interrupt line.
When an interrupt event is detected on an I/O line, and the corresponding bit in IER is written to
one, the GPIO interrupt request line is asserted. A number of interrupt signals are ORed-wired
together to generate a single interrupt signal to the interrupt controller.
The Interrupt Flag Register (IFR) can by read to determine which pin(s) caused the interrupt.
The interrupt bit must be cleared by writing a one to the Interrupt Flag Clear Register (IFRC). To
take effect, the clear operation must be performed when the interrupt line is enabled in IER. Oth-
erwise, it will be ignored.
GPIO interrupts can only be triggered when the CLK_GPIO is enabled.
The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In
this example, this is not the case for the first pulse. The second pulse is however sampled on a
rising edge and will trigger an interrupt request.
Figure 17-4. Interrupt Timing With Glitch Filter Disabled
The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges.
In the example, the first pulse is rejected while the second pulse is accepted and causes an
interrupt request.
Figure 17-5. Interrupt Timing With Glitch Filter Enabled
GPIO_IFR
GPIO_IFR
Pin Level
Pin Level
clock
clock
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