AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 330
AT32UC3B0512AU
Manufacturer Part Number
AT32UC3B0512AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A0128AU.pdf
(2 pages)
5.AT32UC3B0128.pdf
(684 pages)
6.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0512AU
Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512AU-Z2U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
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- AT32UC3B0128 PDF datasheet #6
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21.7.2
Name:
Access Type:
Offset:
Reset Value:
• ONEBIT: Start Frame Delimiter Selector
• MODSYNC: Manchester Synchronization Mode
• MAN: Manchester Encoder/Decoder Enable
• FILTER: Infrared Receive Line Filter
• MAX_ITERATION
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
• DSNACK: Disable Successive NACK
• INACK: Inhibit Non Acknowledge
• OVER: Oversampling Mode
• CLKO: Clock Output Select
• MODE9: 9-bit Character Length
32059L–AVR32–01/2012
ONEBIT
31
23
15
–
7
0: The start frame delimiter is a command or data sync, as defined by MODSYNC.
1: The start frame delimiter is a normal start bit, as defined by MODSYNC.
0: The manchester start bit is either a 0-to-1 transition, or a data sync.
1: The manchester start bit is either a 1-to-0 transition, or a command sync.
0: Manchester endec is disabled.
1: Manchester endec is enabled.
0: The USART does not filter the receive line.
1: The USART filters the receive line by doing three consecutive samples and uses the majority value.
This field determines the number of acceptable consecutive NACK’s when in protocol T=0.
0: Sync pattern according to MODSYNC.
1: Sync pattern according to THR.TXSYNH.
0: NACK’s are handled as normal, unless disabled by INACK.
1: The receiver restricts the amount of consecutive NACK’s by MAX_ITERATION value. If MAX_ITERATION=0 no NACK will be
issued and the first erroneous message is accepted as a valid character, setting CSR.ITER.
0: The NACK is generated.
1: The NACK is not generated.
0: Oversampling at 16 times the baud rate.
1: Oversampling at 8 times the baud rate.
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin unless USCLKS selects the external clock.
0: CHRL defines character length.
Mode Register
CHMODE
CHRL
VAR_SYNC
MODSYNC
30
22
14
MR
Read-write
0x4
0x00000000
6
DSNACK
MAN
29
21
13
5
NBSTOP
USCLKS
FILTER
INACK
28
20
12
4
OVER
27
19
11
–
3
CLKO
PAR
26
18
10
2
MODE
MAX_ITERATION
MODE9
25
17
9
1
SYNC/CPHA
MSBF/CPOL
24
16
8
0
330
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