ED DDR3 1G PCF8000 Samsung Semiconductor, ED DDR3 1G PCF8000 Datasheet - Page 36

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ED DDR3 1G PCF8000

Manufacturer Part Number
ED DDR3 1G PCF8000
Description
Manufacturer
Samsung Semiconductor
Type
DDR3 SDRAMr
Datasheet

Specifications of ED DDR3 1G PCF8000

Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
20ns
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
130mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
K4B1G04(08/16)46E
[ Table 37 ] IDD4W Measurement - Loop Pattern
Note :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 38 ] IDD5B Measurement - Loop Pattern
Note :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
0
1
2
3
4
5
6
7
0
1
2
33...nRFC - 1
13...16
17...20
21...24
25...28
29...32
16-23
24-31
32-39
40-47
48-55
56-63
9...12
8-15
5...8
2,3
6,7
1,2
3,4
0
1
4
5
0
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
repeat cycles 1...4, but BA[2:0] = 1
repeat cycles 1...4, but BA[2:0] = 2
repeat cycles 1...4, but BA[2:0] = 3
repeat cycles 1...4, but BA[2:0] = 4
repeat cycles 1...4, but BA[2:0] = 5
repeat cycles 1...4, but BA[2:0] = 6
repeat cycles 1...4, but BA[2:0] = 7
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
REF
WR
D,D
WR
D,D
D,D
D
D
D
0
1
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
0
1
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1
1
0
0
0
0
0
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0
0
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00
00
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00
00
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0
0
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0
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0
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0
1Gb DDR3 SDRAM
Rev. 1.0 February 2009
0
0
0
F
F
F
0
0
F
0
0
0
0
0
0
0
0
0
00000000
00110011
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