ED DDR3 1G PCF8000 Samsung Semiconductor, ED DDR3 1G PCF8000 Datasheet - Page 17

• Manufacturer Part Number: ED DDR3 1G PCF8000
• Manufacturer: Samsung Semiconductor
• Type: DDR3 SDRAMr

Specifications of ED DDR3 1G PCF8000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 20ns
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 130mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4B1G04(08/16)46E
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach V
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach V
proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
nals, then these ac-levels apply also for the single-ended signals CK and CK .
Note that while ADD/CMD and DQ signal requirements are with respect to V
with respect to V
ended components of differential signals the requirement to reach V
mode characteristics of these signals.
[ Table 11 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU
Notes:
1. For CK, CK use V
2. V
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (V
signal group, then the reduced level applies also here
Specification"
IH
Symbol
(AC)/V
V
V
SEH
SEL
IH
(DC) max, V
IL
(AC) for DQs is based on V
DD
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
IH
/V
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
IL
IL
V
(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use V
(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
DD
V
/2 or V
V
DD
SS
V
V
SEL
or V
SEH
or V
Parameter
DDQ
max
DDQ
SSQ
min
/2
REFDQ
SEH
Figure 3 : Single-ended requirement for differential signals.
min / V
; V
SEH
IH
(AC)/V
SEL
min / V
max [approximately equal to the ac-levels { V
IL
SEL
(AC) for ADD/CMD is based on V
max [approximately the ac-levels { V
Page 17 of 61
SEL
V
SEH
(V
(V
max, V
DD
DD
Note3
Note3
REF
/2)+0.175
/2)+0.175
Min
SEH
, the single-ended components of differential signals have a requirement
min has no bearing on timing, but adds a restriction on the common
DDR3-800/1066/1333/1600
REFCA
; if a reduced ac-high or ac-low level is used for a
IH
IH
(AC) / V
IH
(AC) / V
V
150(AC)/V
SEL
IH
(V
(V
/V
IL
IL
DD
DD
IL
(AC)} for DQ signals] in every half-cycle
(AC) of DQs.
1Gb DDR3 SDRAM
Note3
Note3
Max
/2)-0.175
/2)-0.175
(AC)} for ADD/CMD signals] in every
CK or DQS
IL
Rev. 1.0 February 2009
150(AC) is used for ADD/CMD sig-
time
Unit
V
V
V
V
Notes
1, 2
1, 2
1, 2
1, 2