ED DDR3 1G PCF8000 Samsung Semiconductor, ED DDR3 1G PCF8000 Datasheet - Page 32

• Manufacturer Part Number: ED DDR3 1G PCF8000
• Manufacturer: Samsung Semiconductor
• Type: DDR3 SDRAMr

Specifications of ED DDR3 1G PCF8000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 20ns
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 130mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4B1G04(08/16)46E
[ Table 31 ] Basic IDD and IDDQ Measurement Conditions
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) Read Burst type : Nibble Sequential, set MR0 A[3]=0B
IDD6ET
IDD6TC
IDD7
Symbol
Description
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: see Table 30 ; BL: 8
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Auto Self-Refresh Current (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabled
LOW; CL: see Table 30 ; BL: 8
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 ; BL: 8
Address, Bank Address Inputs: partially toggling according to Table 39 ; Data IO: read data bursts with different data between one burst and the next one
according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output
Buffer and RTT: Enabled in Mode Registers
a)
a)
; AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: Extended Temperature
; AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Auto
f
)
b)
; ODT Signal: stable at 0; Pattern Details: see Table 39
d)
d)
; Self-Refresh Temperature Range (SRT): Normal
; Self-Refresh Temperature Range (SRT): Extended
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f
)
b)
b)
; ODT Signal: MID-LEVEL
; ODT Signal: MID-LEVEL
a)
; AL: CL-1; CS: High between ACT and RDA; Command,
e)
; CKE: Low; External clock: Off; CK and CK:
e)
; CKE: Low; External clock: Off; CK and CK:
1Gb DDR3 SDRAM
Rev. 1.0 February 2009