PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 98
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PEB20534H-10V2.1
Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
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6.1
The DSCC4 provides capability for the PCI host system to access peripherals connected
to the Local Bus Interface (LBI).
Note: The LBI is only available when the DSCC4 is configured for the PCI bus interface
Table 18
Peripheral Type Corresponding
Non-Intelligent
Overview of Transactions:
Standard PCI Slave transactions are used when the PCI host system communicates with
non-intelligent LBI peripherals (single address read/write operations).
For reads, a PCI Retry sequence of operations is performed, in which the DSCC4 will
immediately terminate the PCI transaction (and request a retry) until it terminates the
transaction to the LBI. The DSCC4 uses the retry procedure because the time to
complete the data phase will require more than the maximum allowed 16 PCI clocks
(from the assertion of FRAME to the completion of the first data phase). Data transfer
will be successfully completed within a PCI retry cycle. The number of necessary PCI
retry cycles depend on PCI arbitration behavior and the time it needs to terminate the
transaction on the local bus; PCI TRDY wait states will not be added for the sequential
retry read cycles unless the LBI arbitration time is excessive.
For write transactions, the DSCC4 will store a single data DWORD and then immediately
terminate the PCI transaction successfully. It will then arbitrate the local bus and perform
the write transaction after being granted, depending on the selected number of wait
states and LRDY bus control signal.
Thus write accesses to LBI are performed as ‘posted write’ transactions from the PCI
view. A consecutive write transaction results in PCI retry cycles in the case that the
preceding write transaction is not yet finished on the local bus.
Note: Note that the DSCC4 performs single word PCI Slave read or write transactions
Data Sheet
mode. When in de-multiplexed bus interface mode, the LBI address and data pins
interface to the host system address bus.
only; Slave burst transactions to LBI are not supported.
Local Bus Interface (LBI)
LBI Peripheral Transaction Options
PCI Transaction
Slave
Read
PCI Retry operation
98
Multi Function Port (MFP)
Write
PCI posted write
operation
PEB 20534
PEF 20534
2000-05-30
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