PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 160

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

– In ASYNC mode, a bus configuration is not recommended.
Note: In high speed operation the usage of bus configuration is not supported.
Prerequisites for bus operation are:
• NRZ encoding
• ‘OR’ing of data from every transmitter on the bus (this can be realized as a wired-OR,
• Feedback of bus information (CxD input).
The bus configuration is selected via register CCR0.
Note: Central clock supply for each station is not necessary if both the receive and
The bus configuration mode operates independently of the clock mode, e.g. also
together with clock mode 1 (receive and transmit strobe operation).
7.7.1
The idle state of the bus is identified by eight or more consecutive ‘1’s. When a device
starts transmission of a frame, the bus is recognized to be busy by the other devices at
the moment the first ‘zero’ is transmitted (e.g. first ‘zero’ of the opening flag in
HDLC mode).
After the frame has been transmitted, the bus becomes available again (idle).
Note: If the bus is occupied by other transmitters and/or there is no transmit request in
7.7.2
During the transmission, the data transmitted on TxD is compared with the data on CxD.
In case of a mismatch (‘1’ sent and ‘0’ detected, or vice versa) data transmission is
immediately aborted, and idle (logical ‘1’) is transmitted.
HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the
first part of the frame is still present in the SCC transmit FIFO. If not, an XMR interrupt is
generated.
Since a ‘zero’ (‘low’) on the bus prevails over a ‘1’ (high impedance) if a wired-OR
connection is implemented, and since the address fields of the HDLC frames sent by
different stations normally differ from one another, the fact that a collision has occurred
will be detected prior to or at the latest within the address field. The frame of the
transmitter with the highest temporary priority (determined by the address field) is not
affected and is transmitted successfully. All other stations cease transmission
immediately and return to bus monitoring state.
Data Sheet
using the TxD open drain capability)
transmit clock is recovered by the DPLL (clock modes 3a, 7a). This minimizes the
phase shift between the individual transmit clocks.
the SCC, logical ‘1’ will be continuously transmitted on TxD.
Serial Bus Access Procedure
Serial Bus Collisions and Recovery
Serial Communication Controller (SCC) Cores
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PEB 20534
PEF 20534
2000-05-30