PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 157
PEB20534H-10V2.1
Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
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Figure 53
Figure 54
To supervise correct function when using bi-phase encoding, a status flag and a
maskable interrupt inform about synchronous/asynchronous state of the DPLL.
Data Sheet
DPLL
Count
Correction
Transmit
Clock
Receive
Clock
DPLL
Count
Correction
DPLL
Output
DPLL Algorithm for NRZ and NRZI Encoding
with Phase Shift Disabled (CCR0:PSD = ‘1’)
DPLL Algorithm for FM0, FM1 and Manchester Coding
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0
+PA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0
Bit Cell (FM Coding)
- ignore -
+PA
Serial Communication Controller (SCC) Cores
157
Bit Cell (Manchester Coding)
Bit Cell
-PA
0
-PA
0
1
+PA
2
3
ITD04820
4
- ignore -
PEB 20534
PEF 20534
5
0
ITD01807
2000-05-30
6
7
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