PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 42

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 4
Pin No.
147
149
164
151
152
153
160
Data Sheet
Symbol
LHLDA
LCSO
LALE
LRD
LWR
LBHE
LRDY
Local Bus Interface (LBI) / General Purpose Port (GPP) /
Synchronous Serial Control (SSC) Interface Pins
Input (I)
Output (O)
I/O
O
(I)/O
(I)/O
(I)/O
(I)/O
I
Function
LBI Hold Status
The function depends on whether DSCC4 is
enabled as arbitration master via bit
LCONF.HDEN:
As an output, LHLDA = ’0’ confirms that the
LBI bus is in HOLD mode (arbitration master).
As an input, LHLDA = ’1’ means that DSCC4
must remain in hold mode (external arbiter).
A Pull-Up resistor to V
LBI is not used.
LBI Chip Select Output
Used to select LBI external peripheral
LBI Address Latch Enable
This pin is tri-state when unused. A Pull-Down
resistor to V
used or operated in demultiplexed LBI
configuration.
LBI Read strobe
This pin is tri-state when the LBI is not the
active bus master. Refer to
timing figures.
LBI Write strobe
This pin is tri-state when the LBI is not the
active bus master. Refer to
timing figures.
LBI Byte high enable
This pin is tri-state when the LBI is not the
active bus master. Refer to
timing figures.
LBI Ready strobe
Control signal for extended bus cycles. This
signal is asserted by the bus target to insert
wait states.
42
SS
is recommended if LBI is not
DD3
is recommended if
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Pin Descriptions
PEB 20534
PEF 20534
2000-05-30
for
for
for