PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 183
PEB20534H-10V2.1
Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
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Note: The broadcast address may be programmed in bit field RAL2 if broadcasting is
The primary station has to operate in transparent HDLC mode.
Reception of Frames:
The reception of frames functions similarly to the LAPB/LAPD operation (see
Duplex LAPB/LAPD Operation” on Page
Transmission of Frames:
The SCC does not transmit S-, or I-frames if not instructed to do so by the primary station
via an S-, or I-frame with the poll bit set.
The SCC can be prepared to send an I-frame by the host by setting bit ’SXIF’ in register
CCR2. The transmission of the frame, however, will not be initiated by the SCC until
reception of either an
• RR, or
• I-frame
with poll bit set (p = ‘1’).
After the frame has been transmitted (with the final bit set), the host has to wait for an
ALLS or XMR interrupt.
Since the on-chip timer of the SCC must be operated in the external timer mode
(a secondary does not poll the primary for acknowledgements), timer supervision must
be done by the primary station.
Upon the arrival of an acknowledgement the SCC transmit FIFO is enabled and an
interrupt is forwarded to the host, either the
– message has been positively acknowledged (ALLS interrupt), or the
– message must be repeated (XMR interrupt).
Additionally, the timer can be used under host control to provide timer recovery of the
secondary if no acknowledgements are received at all.
Note: A secondary will transmit transparent frames only if the permission to send is
Examples:
A few examples of SCC/host interaction in the case of normal response mode (NRM)
mode are shown in figure 68 and 68.
Data Sheet
required.
In this case bit fields RAL1 and RAL2 are not equal.
given by receiving an S-frame or I-frame with poll bit set (p = ‘1’).
183
177).
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30
“Full-
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