PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 415

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

13.6.1.3 PCI Timing Characteristics
When the DSCC4 operates as a PCI Master (initiator) and it either reads or writes a burst
– as controlled by the on-chip DMA controller – it does not deactivate IRDY between
consecutive data. In other words, no wait states are inserted by the DSCC4 as a
transaction initiator. The numbers of wait states, inserted by the DSCC4 as initiator are
listed in
Table 116
Transaction
Memory read burst
Memory write burst
Fast Back-to-back burst;
1st transaction
Fast Back-to-back burst;
2nd and subsequent
transactions
When the DSCC4 operates as a PCI Slave (target), it inserts wait cycles by deactivating
TRDY. The numbers of wait states, typically inserted by the DSCC4 are listed in
Table
Table 117
Transaction
Configuration read
Configuration write
Register read
Register write
LBI read
LBI write
The number of wait states inserted by the DSCC4 as target is not critical because
accesses to/via the DSCC4 are usually kept to a minimum in a system.
Data Sheet
116:
Table
Number of Wait States Inserted by the DSCC4 as Initiator
Number of Wait States Inserted by the DSCC4 as Slave
116.
1st Data Cycle
0
0
0
1
415
Number of Wait States
2
0
3
0
3
0
Number of Wait States
2nd and Subsequent Data Cycles
0
0
0
0
Electrical Characteristics
PEB 20534
PEF 20534
2000-05-30