PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 55

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Figure 10
When in De-multiplexed bus configuration, the DSCC4 adheres the PCI bus protocol and
timing specificaton, except for the address and command handling. In this mode, the
addresses are provided on a separate address bus A(31:2) to eliminate the need for
external de-multiplexing buffers. The address lines A(31:2) correspond to the address
lines AD(31:2) in PCI mode. The address becomes valid with the falling edge of FRAME
and stays valid for the standard PCI address phase, the turn-around cycle and the entire
data phase. In burst mode the addresses have to be incremented externally for each
single transfer.
Moreover, in De-multiplexed mode the command signals are not used. Instead of the
command signals a separate pin W/R (I/O) provides the Write/Read strobe signal. The
Write/Read becomes valid with the falling edge of FRAME and stays valid for the
standard PCI address phase, the turn-around cycle and the entire data phase.
Data Sheet
FRAME
D(31:0)
BE(3:0)
A(31:2)
TRDY
W/R
CLK
Master Burst WRITE/READ Transaction in
De-multiplexed Configuration
0ns
don't care
don't care
ADDR,
BE(3:0)
WRITE/READ Access
DATA1
ADDR
DATA2
BE(3:0)
55
100ns
BE(3:0)
DATA3
Microprocessor Bus Interface
BE(3:0)
DATA4
200ns
PEB 20534
PEF 20534
2000-05-30