H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 87

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
Data Setup, Hold and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS
(base) and tDH (base) value (see Table 15) to the DtDS and DtDH (see Table 16) derating value respectively. Example:
tDS (total setup time) = tDS (base) + DtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
first crossing of V
crossing of V
nal slew rate line between shaded ‘V
later than the nominal slew rate line anywhere between shaded ‘V
the actual signal from the ac level to dc level is used for derating value (see Figure 9).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
first crossing of V
crossing of V
slew rate line between shaded ‘dc level to V
earlier than the nominal slew rate line anywhere between shaded ‘dc to V
the actual signal from the dc level to V
For a valid transition the input signal has to remain above/below V
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach V
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 15 - Data Setup and Hold Base-Values
Note: (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS-slew rate)
Units [ps]
tDH (base)
tDS (base)
REF(dc)
IH(dc)
IH(ac)
REF(dc)
min and the first crossing of V
and the first crossing of V
min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
. Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last
800MHz
10
45
REF(dc)
REF(dc)
to ac region’, use nominal slew rate for derating value. If the actual signal is
REF(dc)
IL(ac)
level is used for derating value (see figure 9).
REF(dc)
max (see Figure 7). If the actual signal is always earlier than the nomi-
region’, use nominal slew rate for derating value. If the actual signal is
(see Figure 8). If the actual signal is always later than the nominal
900MHz
45
0
REF(dc)
IH/IL(ac)
to ac region’, the slew rate of a tangent line to
REF(dc)
for some time t
region’, the slew rate of a tangent line to
1.0GHz
TBD
TBD
VAC
(see Table 17).
H5TQ2G63BFR
IL(dc)
reference
V
V
REF(dc)
IH/L(ac)
IH/L(dc)
max and the
and the
IH/IL(ac)
IH/IL(ac)
87
.