H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 11

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
1.5 Programming the Mode Registers
For application flexibility, various functions, features and modes are programmable in four Mode Registers,
provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register
Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode
Registers must be fully initialized and/or re-initialized, i.e. written, after power-up and/or reset for proper oper-
ation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during nor-
mal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of
the MRS fields, all address fields within the accessed mode register must be redefined when the MRS com-
mand is issued. MRS command and DLL Reset do not affect array contents, which means these commands
can be executed any time after power-up without affecting the array contents.
The mode register set command cylce time, tMRD is required to complete the write operation to the mode
regsiter and is the minimum time required between two MRS commands shown in Figure 4.
The MRS command to Non-MRS command delay, tMOD, is required for the DRAM to update the features,
except DLl reset, adn is the minimum time required from an MRS command to a non-MRS command exclud-
ing NOP and DES shown in Figure 5.
ADDRESS
Setting
CMD
ODT
ODT
CKE
CK#
CK
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISENABLED prior and/or after MRS command
VALID
VALID
VALID
VALID
T0
VALID
VALID
VALID
VALID
Old Settings
T1
VALID
VALID
VALID
T2
ODTLoff+1
VALID
VALID
MRS
Ta0
Figure 4. tMRD Timing
/DES
VALID
VALID
NOP
Ta1
tMRD
/DES
VALID
VALID
NOP
Tb0
Updating Settings
VALID
VALID
MRS
Tb1
VALID
VALID
/DES
NOP
Tb2
tMOD
TIME BREAK
/DES
VALID
VALID
NOP
Tc0
VALID
VALID
VALID
Tc1
H5TQ2G63BFR
New Settings
DON’T CARE
VALID
VALID
VALID
VALID
Tc2
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