H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 16

58T1898

H5TQ2G63BFR-H9C

Manufacturer Part Number
H5TQ2G63BFR-H9C
Description
58T1898
Manufacturer
HYNIX SEMICONDUCTOR
Datasheet

Specifications of H5TQ2G63BFR-H9C

Memory Type
SDRAM
Memory Configuration
128M X 16
Access Time
13.5ns
Interface Type
CMOS
Memory Case Style
FBGA
No. Of Pins
96
Operating Temperature Range
0°C To +85°C
Memory Size
2 Gbit
Rohs Compliant
Yes

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Rev. 0.5 / Aug. 2010
*1 : BA2 and A8, A10, and A13~A15 are RFU and must be programmed to 0 during MRS.
1.7 Mode Register MR1
The Mode Register MR1 stores the data for enabling of disabling the DLL, output driver strength, Rtt_Nom
impedance, additive latency, Write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by
asserting low on CS, RAS, CAS, WE, high on BA0 and low on BA1 and BA2, while controlling the states of
address pins according to Figure 7.
BA
0*
1
2
*2: Outputs disabled - DQs, DQSs, DQS#s.
BA
0
0
1
1
A
0
A11
BA1
A7
0
1
0
1
0
0
1
1
4
1
A
0
1
BA
12
1
0
A
0
1
0
1
Write leveling enable
3
A
BA0
15 ~
0
1
0
1
0*
1
A
TDQS enable
Additive Latency
13
0 (AL disabled)
Output buffer enabled
Output buffer disabled
Disabled
Enabled
Disabled
Enabled
Reserved
Qoff
A
12
CL-1
CL-2
MR Select
TDQS
A
Qoff
MR0
MR1
MR2
MR3
11
A
*2
0*
10
1
Rtt_Nom
A
9
Note: RZQ = 240Ω
*3: In Write leveling Mode (MR1[bit7]=1) with
MR1[bit12]=1, all RTT_Nom settings are allowed; in
Write
MR1[bit12]=0, only RTT_Nom settings of RZQ/2,
RZQ4 and RZQ/6 are allowed.
*4: If RTT_Nomm is used during Writes, only the val-
ues RZQ/2,RZQ/4 and RZQ/6 are allowed.
*2
A9
0
0
0
0
1
1
1
1
A
0*
8
1
Figure 7. MR1 Definition
Leveling
0
0
1
1
0
0
1
1
A6
Level
A
7
0
1
0
1
0
1
0
1
A2
Rtt_Nom
A
6
Mode
Note: RZQ= 240Ω
D.I.C
Rtt_Nom disabled
A
A5
0
0
1
1
5
Reserved
Reserved
Rtt_Nom
(MR1[bit7]=1)
RZQ/12
RZQ/4
RZQ/2
RZQ/6
RZQ/8
A
0
1
0
1
A1
4
AL
A
*4
Output Driver Impedence Control
3
*4
*3
Rtt_Nom
A
2
with
D.I.C
A
1
RZQ/TBD
RZQ/TBD
RZQ/6
RZQ/7
A
0
1
DLL
A
0
0
H5TQ2G63BFR
Address Field
Mode Register 1
DLL Enable
Disable
Enable
16

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