H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 74

58T1898

H5TQ2G63BFR-H9C

Manufacturer Part Number
H5TQ2G63BFR-H9C
Description
58T1898
Manufacturer
HYNIX SEMICONDUCTOR
Datasheet

Specifications of H5TQ2G63BFR-H9C

Memory Type
SDRAM
Memory Configuration
128M X 16
Access Time
13.5ns
Interface Type
CMOS
Memory Case Style
FBGA
No. Of Pins
96
Operating Temperature Range
0°C To +85°C
Memory Size
2 Gbit
Rohs Compliant
Yes

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Rev. 0.5 / Aug. 2010
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 61 apply to Table : a
Auto precharge write
recovery + precharge
time
End of MPR Read
burst to MSR for
MPR (exit)
ACTIVE to
PRECHARGE
command period
ACTIVE to ACTIVE
command period for
2KB page size
Four activate window
for 2KB page size
Command and
Address setup time
to CK, CK referenced
to Vih (ac) / Vil (ac)
levels
Command and
Address hold time
from CK, CK
referenced to Vih (dc)
/ Vil (dc) levels
Calibration Timing
Power-up and
RESET calibration
time
Normal operation Full
calibration time
Normal operation
Short calibration time
Reset Timing
Exit Reset from CKE
HIGH to a valid
command
Self Refresh
Timings
Exit Self Refresh to
commands not
requiring a locked
DLL
Exit Self Refresh to
commands requiring
a locked DLL
Minimum CKE low
width for Self Refresh
entry to exit timing
Parameter
tDAL (min)
tIH (base)
tIS (base)
tZQoper
tCKESR
Symbol
tXSDLL
tMPRR
tZQCS
tZQinit
tRRD
tFAW
tRAS
tXPR
tXS
tDLLK(min
tRFC(min)
tRFC(min)
max(5nsC
max(5nsC
tCKE(min)+1nCK
+10ns)
+10ns)
37.5
42.5
Min
120
512
256
24
45
64
K,
K,
1
7
)
800MHz
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
tDLLK(min
max(5nsC
tRFC(min)
max(5nsC
tRFC(min)
tCKE(min)+1nCK
+10ns)
+10ns)
35.6
41.1
Min
110
512
256
28
35
64
K,
K,
1
7
)
900MHz
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
tDLLK(min
tRFC(min)
tRFC(min)
tCKE(min)
max(5nsC
max(5nsC
+10ns)
+10ns)
+1nCK
Min
100
512
256
31
34
40
25
64
K,
K,
1
7
)
1.0GHz
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H5TQ2G63BFR
Units Notes
nCK
nCK
nCK
nCK
nCK
nCK
ns
ps
ps
b, 16
b, 16
22
23
e
e
e
74

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