H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 54

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
8. IDD and IDDQ Specification Parameters and Test Conditions
8.1 IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the
setup and test load for IDD and IDDQ measurements.
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For IDD and IDDQ measurements, the following definitions apply:
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IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3
SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the
DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to sup-
port correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ
cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
”0” and “LOW” is defined as VIN <= V
”1” and “HIGH” is defined as VIN >= V
“FLOATING” is defined as inputs are VREF - VDD/2.
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1 on Page 39.
Basic IDD and IDDQ Measurement Conditions are described in Table 2 on page 42.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 on page 42 through Table 10 on page
47.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or
IDDQ measurement is started.
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
B
(Output Buffer enabled in MR1);
ILAC(max).
IHAC(max).
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