TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 164

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

The E1 Byte sent to the Rx Terminal Port may optionally be used to communicate an in-band AIS Indication.
This is controlled by command RA2E (CR11; 1FB[H], Bit 2). When Enabled:
If the conditions are such that the E1 Alarm will be inserted (if enabled by RA2E) it will be indicated by the set-
ting of RPAISC or RLAISC.
RX TERMINAL OUTPUTS
The Receive Side Signal Outputs from the Rx Terminal Port are RTDO (Serial Data), RTCO (serial Clock),
TPCO (Parallel Clock), TPDO0-TPDO7 (Parallel Data), RSPE (Payload Indication), RSYN (Sync Pulse) and
TPARO (odd Parity). Parity errors can be created with SBPE (CR3; 0FB[H], Bit 4). One additional output
TPDVO and two additional inputs TPDVI0 and TPDVI1 are optionally used in 19.44 Mbyte/s Multiplexed Bus
configurations to prevent bus collisions. When employed, bus collisions are reported as RBUSCOL (SR1;
0F2/3/5[H], Bit 1).
Two Alarm Port pins RSF (Rx Signal Fail) and RAIS (Rx AIS) are used to provide an external indication of
Receive Side anomalies.
TX TERMINAL INPUTS
The Inputs to the Tx Terminal Port are TTDI (Serial Data), TPDI0-TPDI7 (Parallel Data) and TPARI (odd Par-
ity). Four other pins TTCI/O (Serial Clock), TPCI/O (Parallel Clock), TSPEI/O (Payload Indication) and
TSYNI/O (Sync Pulse) are bidirectional. In SONET or SPE-only Modes they are inputs. In Datacom mode they
are outputs. Failures at the Tx Terminal Port are indicated by TLOC (SR2; 1F0/1/4[H], Bit 7), TLOS (SR2;
1F0/1/4[H], Bit 0) and TBPE (SR5; 1E8/9/C[H], Bit 7). Parity checking can be disabled with DISTBPE (CR10;
1FA[H], Bit 4).
The Alarm Port input pin TAIS can be used to force an AIS condition at the Tx Line output. Pin TAIS at the Low
level results in the setting of TAISV (SR4; 1F2/3/5[H], Bit 3).
TX TERMINAL OVERHEAD PROCESSING
The Tx Terminal Port and Tx TOH Processing Blocks are responsible for Signal Failure Detection, Frame Delin-
eation, Overhead Distribution and Overhead Processing. The Tx Terminal Port routes the C1, B1, E1, F1, D1,
D2, D3, B2, K1, K2, D4, D5, D6, D7, D8, D9, D10, D11, D12, Z1, Z2 and E2 Bytes to the ISC Port if SPE-only
Mode is not enabled.
1. The Setting of RRE1 (in Line Timing Mode) will be disregarded.
2. The normal state of the E1 Byte will be all "0".
3. The occurrence of certain anomalies will result in the E1 Byte being set to all "1".
Proprietary TranSwitch Corporation Information for use Solely by its Customers
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DATA SHEET
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1