DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 436
DK-SI-5SGXEA7/ES
Manufacturer Part Number
DK-SI-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-SI-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2724
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2–20
Stratix V Device Handbook Volume 3: Transceivers
Figure 2–16
opposed to a maximum of five as shown in
ATX PLL is used as a transmit PLL instead of a channel PLL in the transceiver bank.
Using the ATX PLL frees the channel PLLs of both channels 1 and 4 to be configured
as CDRs to perform receiver operations.
shows all six channels in the transceiver bank in bonded configuration, as
Figure
Chapter 2: Transceiver Clocking in Stratix V Devices
2–15. This is possible because the
May 2011 Altera Corporation
Internal Clocking
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