DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 391

• Manufacturer Part Number: DK-SI-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-SI-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2724

Chapter 1: Transceiver Architecture in Stratix V Devices
Standard PCS Architecture
May 2011 Altera Corporation
f
1
Each transceiver standard PCS consists of a transmitter channel and a receiver
channel.
The receiver channel consists of the following components:
■
■
■
■
■
■
The transmitter channel consists of the following components:
■
■
■
Each transceiver channel interfaces to the PCIe hard IP block, the PIPE interface for
soft IP implementations of PCIe, or directly to the FPGA fabric (FPGA
fabric-transceiver interface). The transceiver channel interfaces to the PCIe hard IP
block if you use the hard IP block to implement the PCIe PHY MAC, data link layer,
and transaction layer. Otherwise, the transceiver channel interfaces directly to the
FPGA fabric.
The PCIe hard IP-transceiver interface is outside the scope of this chapter. This
chapter describes the FPGA fabric-transceiver interface only. For more information,
refer to the “PCI Express PHY IP Core” chapter in the
Guide
The standard transceiver channel datapath can be divided into two configurations
based on the FPGA fabric-transceiver interface width (channel width) and the
transceiver channel PMA-PCS width (serialization factor):
■
■
The standard transceiver channel datapath does not support the quadruple-width
configuration.
“Word Aligner” on page 1–20
“Rate Match (Clock Rate Compensation) FIFO” on page 1–24
“8B/10B Decoder” on page 1–25
“Byte Deserializer” on page 1–26
“Byte Ordering Block” on page 1–27
“Receiver Phase Compensation FIFO” on page 1–28
“Transmitter Phase Compensation FIFO” on page 1–29
“Byte Serializer” on page 1–29
“8B/10B Encoder” on page 1–30
Single-width configuration
Double-width configuration
and to the
PCI Express Compiler User
Guide.
Stratix V Device Handbook Volume 3: Transceivers
Altera Transceiver IP Core User
1–19