DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 218

• Manufacturer Part Number: DK-SI-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-SI-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2724

Table 6–1. LVDS Channels Supported in Stratix V GX Devices
Output Buffers,
Emulated LVDS
Notes to
(1) The LVDS channel count does not include dedicated clock input pins.
(2) The number of LVDS receiver (RX) and transmitter (TX) channels are preliminary.
(3) For more information about the clock region, refer to the
Output buffers,
I/O Bank Side
Clock Region
Input Buffers,
True LVDS
True LVDS
Device
eTX
RX
TX
(3)
Table
6–1:
42 39 42 39 42 39 42 39 54 51 54 51 54 51 54 51 47 43 47 43 47 43 47 43 42 39 42 39 42 39 42 39
42 39 42 39 42 39 42 39 54 51 54 51 54 51 54 51 53 49 53 43 53 49 53 43 42 39 42 39 42 39 42 39
84 78 84 78 84 78 84 78
Top
5SGXA3
Table 6–1
I/Os as true LVDS buffers or emulated LVDS buffers, as long as the combination of the two do not exceed the maximum count.
Bottom
through
Top
5SGXA4
Table 6–3
Bottom
“Fractional PLLs and Stratix V Clocking” on page
list the maximum number of LVDS I/Os supported in Stratix V devices. You can design the LVDS
Top
5SGXA5
(Note
Bottom
1), (2)—Preliminary
Top
5SGXA7
Bottom
6–22.
Top
5SGXA9
92
Bottom
92
Top
5SGXAB
92
Bottom
92 84 78 84 78 84 78 84 78
Top
5SGXB5
Bottom
Top
5SGXB6
Bottom