DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 128
DK-SI-5SGXEA7/ES
Manufacturer Part Number
DK-SI-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-SI-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2724
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3–12
Figure 3–7. Two 16 x 16 Independent Multiplier Mode or Two 18 x 18 Independent Partial Multiplier Mode for Stratix V
Devices
Notes to
(1) The inputs for 16-bit independent multiplier mode are data[15..0]. The unused input bits require padding with zero.
(2) For 18-bit independent multiplier mode, only 32-LSB output for both multipliers are routed to the output register.
Figure 3–8. One 27 x 27 Independent Multiplier Mode for Stratix V Devices
Note to
(1) The result can be up to 64-bits when combined with a chainout adder/accumulator.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure
Figure
(Note
3–8:
3–7:
dataa_b0[26..0]
dataa_a0[26..0]
1),
(2)
dataa_1[ ]
datab_1[ ]
datab_0[ ]
dataa_0[ ]
27
27
Variable Precision DSP Block
Variable Precision DSP Block
Mult_L
Mult_H
Multiplier
x
x
x
Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
(Note 1)
54
result_1[ ]
result_0[ ]
Operational Mode Descriptions
May 2011 Altera Corporation
Result[53..0]
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