DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 173
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
DK-SI-5SGXEA7/ES
Manufacturer Part Number
DK-SI-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-SI-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2724
- Current page: 173 of 530
- Download datasheet (16Mb)
Chapter 4: Clock Networks and PLLs in Stratix V Devices
Document Revision History
Document Revision History
Table 4–5. Document Revision History
May 2011 Altera Corporation
May 2011
December 2010
July 2010
Date
Programmable Duty Cycle
Version
The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle
setting is achieved by a low and high time-count setting for the post-scale counters. To
determine the duty cycle choices, the Quartus II software uses the frequency input
and the required multiply or divide rate. The post-scale counter value determines the
precision of the duty cycle. The precision is defined as 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, steps of 5% are possible for
duty-cycle choices from 5% to 90%.
If the PLL is in external feedback mode, set the duty cycle for the counter driving the
fbin pin to 50%. Combining the programmable duty cycle with programmable phase
shift allows the generation of precise non-overlapping clocks.
Table 4–5
1.2
1.1
1.0
■
■
■
■
■
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
Chapter moved to volume 2 for the 11.0 release.
Updated
Updated
Figure
Updated
Added
lists the revision history for this chapter.
4–18,
“PLL Clock Outputs”
Table
Figure
“Zero-Delay Buffer Mode”
Figure
4–1.
4–3,
4–20,
Figure
Figure
4–4,
section.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure
4–25, and
and
Changes
4–5,
“External Feedback Mode”
Figure
Figure
4–28.
4–6,
Figure
4–15,
sections.
Figure
4–17,
4–33
Related parts for DK-SI-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: