DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 499
DK-SI-5SGXEA7/ES
Manufacturer Part Number
DK-SI-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-SI-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2724
- Current page: 499 of 530
- Download datasheet (16Mb)
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
XAUI
Figure 4–32. XAUI Clocking Diagram
May 2011 Altera Corporation
xgmii_tx_clk
xgmii_rx_clk
Channel 0
Channel 1
Channel 2
Channel 3
16
Transceiver Clocking
16
Parallel Clock
20
Figure 4–32
One of the two channel PLLs in a transceiver bank generates the transmitter serial and
parallel clocks for the four XAUI channels. The ×6 clock line carries the transmitter
clocks to the PMA and PCS of each of the four channels.
Table 4–8
width, and interface frequency supported in a XAUI configuration.
Table 4–8. Input Reference Clock Frequency and Interface Speed Specifications for XAUI
Configurations
from Channel 0
Parallel Clock
(Recovered)
FPGA Fabric
Input Reference Clock
Frequency (MHz)
lists the input reference clock frequency, FPGA fabric-transceiver interface
156.25
CMU PLL
shows transceiver clocking in a XAUI configuration.
(From the ×1 Clock Lines)
Soft PCS
20
Soft PCS
Soft PCS
Soft PCS
Serial Clock
Central/ Local Clock Divider
FPGA Fabric-Transceiver
16-bit data, 2-bit control
Channel 0
Channel 1
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Channel 2
Channel 3
Interface Width
20
20
Clock Divider
Stratix V Device Handbook Volume 3: Transceivers
/2
/2
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Receiver Standard PCS
Transmitter Standard PCS
Parallel Clock (Recovered)
Parallel Clock
FPGA Fabric-Transceiver
10
10
Interface Width (MHz)
156.25
Transmitter PMA Ch 0
Transmitter PMA Ch 1
Transmitter PMA Ch 2
Transmitter PMA Ch 3
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Receiver PMA
4–43
Related parts for DK-SI-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: