DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 172

• Manufacturer Part Number: DK-SI-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-SI-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2724

4–32
Figure 4–28. External Feedback Mode in Stratix V Devices
Notes to
(1) EFB mode can support two single-ended or one differential feedback inputs. For more information, refer to
(2) Only one of the two VCOs can support differential EFB mode at one time while you can use the other VCO for general purpose clocking.
(3) External board connection for one differential clock output and one differential feedback input for differential EFB support.
(4) External board connection for two single-ended clock outputs and two single-ended feedback inputs for single-ended EFB support.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
inclk
inclk
Figure
Clock Multiplication and Division
÷n
÷n
4–28:
PFD
PFD
Figure 4–28
Each Stratix V PLL provides clock synthesis for PLL output ports using
M/(N  post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor, n, and is then multiplied by the m feedback factor. The control loop drives the
VCO to match f
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output frequencies
that meets its frequency specifications. For example, if the output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range). Then the
post-scale counters scale down the VCO frequency for each output port.
Each PLL has one pre-scale counter, N, and one multiply counter, M, with a range of
1 to 512 for both M and N. The N counter does not use duty-cycle control because the
only purpose of this counter is to calculate frequency division. The post-scale counters
range from 1 to 512 with a 50% duty cycle setting. The high- and low-count values for
each counter range from 1 to 256. The sum of the high- and low-count values chosen
for a design selects the divide value for a given counter.
The Quartus II software automatically chooses the appropriate scaling factors
according to the input frequency, multiplication, and division values entered into the
Altera
CP/LF
CP/LF
®
PLL megafunction.
VCO 0
VCO 1
(2)
(2)
shows external feedback mode implementation in Stratix V devices.
in
(M/N). Each output port has a unique post-scale counter that
C10
C11
C12
C13
C14
C15
C16
C17
m0
m1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
20
mux
4
(Note 1)
EXTCLKOUT[0]
EXTCLKOUT[1]
EXTCLKOUT[2]
EXTCLKOUT[3]
Chapter 4: Clock Networks and PLLs in Stratix V Devices
fbout0
fbin[p]
fbin1
fbout1
fbout[p]
fbin0
fbout[n]
fbin[n]
Figure 4–20 on page
May 2011 Altera Corporation
(4)
(4)
(3)
4–24.
Stratix V PLLs
(3)
external
board
trace