TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 54

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

2. VME Interface > VME Slave
2.2.1.3
2.2.1.4
54
3. Once the transaction completes on the VME bus (that is, all the data is placed within the
4. After arbitration by the Linkage Module, the command and address information, as well
5. The PCI/X Master completes the write transaction to the PCI/X target.
VME Slave Read-Modify Write (RMW) Cycles
The Tsi148 VME Slave responds to RMW cycles. The VME Slave does not complete
VMEbus RMW cycles as indivisible cycles on the PCI/X bus. The PCI/X bus LOCK_ signal
is not supported by the Tsi148 PCI/X Master and therefore the read and write cycles are
divisible on the PCI/X bus.
For information on how Tsi148 generates RMW cycles as a VME Master, refer to
Section 2.3.3 on page
Terminations
The VME Slave can terminate a SCT, BLT, or MBLT cycle with a DTACK_ signal or a
RETRY_ signal. The VME Slave never terminates a SCT, BLT, or MBLT cycle with a
BERR_ signal.
All 2eVME and 2eSST cycles are terminated with a normal termination or retry signal. The
VME Slave never terminates a 2eVME or 2eSST cycle with a slave termination or error
termination.
VME Slave’s write buffer data queue) the VME Slave sends a request to the Linkage
Module.
as the write data, is passed to the PCI/X Master’s write command and data queue.
— The PCI/X Master’s write buffer data queue is 4 Kbytes and the command queue
(which is used to store commands from Linkage Module) is six entries deep.
56.
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13