TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 120
![IC PCI-VME BRIDGE 456PBGA](/photos/6/93/69324/tsi148-133il_sml.jpg)
TSI148-133IL
Manufacturer Part Number
TSI148-133IL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133IL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
800-1905
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5. Resets, Clocks, and Power-up Options > Resets
120
•
Reset Outputs
— VMEbus System Reset Out (SRSTO): This signal is used to reset the VMEbus.
— Local Bus (PCI/X) Reset Out (LRSTO_): This signal resets local (PCI/X) resources.
Typically, this signal is connected to the backplane SYSRESET_ signal through an
inverting open collector buffer. When SRSTO is asserted, the VMEbus SYSRESET_
signal is asserted.
SRSTO can be asserted either through hardware or software events. The hardware
reset events are detailed in
setting the SRESET bit in the VMEbus Control (VCTRL) register (see
Section 10.4.34 on page
The SRESET bit is self-clearing if SRSTI is connected to SRSTO through a
transceiver.
LRSTO_ can be combined with other board sources to generate a local (PCI/X) reset
signal.
LRSTO_ can be asserted either through hardware or software events. The hardware
reset events are detailed in
by the following methods:
If the SRESET bit is set, the Tsi148 asserts SRSTO output even if it is not the
system controller.
The SRSTO signal is asserted for a minimum of 200ms.
253).
Figure
Figure
30. The signal can be asserted through software by
30. This signal can be asserted through software
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
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