TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 129

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

5.4.2.3
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Auto Slot ID Enable
The Auto Slot ID Enable (ASIDEN) feature is controlled through a power-up option. The
ASIDEN feature allows the CR/CSR base address to be configured using the Auto Slot ID
protocol. ASIDEN can be enabled through a power-up option (shown in
page
System Failure Auto Slot ID (SFAILAI) Configuration
The System Failure Auto Slot ID (SFAILAI) bit is used when the Auto Slot ID protocol is
enabled in the system to assign the CR/CSR base address. The initial value of the SFAILAI
bit can be configured at power-up reset through the SFAILAI_AC power-up option or a value
can be programmed by software in the SFAILAI bit in the VMEbus Control register
(VCTRL) (see
When Auto Slot ID is used to assign the CR/CSR base address, the SFAILAI bit is set by the
assertion of the SRSTI_ signal. The SFAILAI bit must be cleared in order for Tsi148’s System
Fail Output (SFAILO) signal to be negated. SFAILO is automatically negated if the
SFAILAI_AC power-up option is selected, otherwise SFAILO is negated when software
clears the SFAILAI bit in the VCTRL register.
This feature can be enabled through the SFAILAI_AC power-up option as shown in
on page
Geographic Slot ID Enable
The Geographic Slot ID Enable function initializes the CR/CSR base address register using
the VMEbus GA signals. The Geographic Slot ID Enable feature allows a board to come out
of reset with the CR/CSR registers visible from the VMEbus and the base address of the
CR/CSR is determined by the VMEbus GA signals.
The initial value of the CR/CSR Enable bit in the CR/CSR Attribute (CRAT) register and
CBAR bits in the CR/CSR Base Address (CBAR) register can be configured at power-up
reset using the Geographic Slot ID Enable function (see
signal is zero at the rising edge of the PURSTI_ signal, the CR/CSR enable bit and CBAR bits
are cleared. If the VD[3] signal is one at the rising edge of the PURSTI_ signal, the CR/CSR
enable bit is set and the CBAR bits 7 to 3 are set to the inverted value of the VMEbus
geographic address signals. When the SRSTI_ signal is asserted, the CR/CSR EN bit and the
CBAR bits are loaded with the power-up option reset values.
126). The power-up option is sampled at the rising edge of the PURSTI_ signal.
126. The power-up option is sampled at the rising edge of the PURSTI_ signal.
Section 10.4.34 on page
253).
5. Resets, Clocks, and Power-up Options > Power-up Options
Table 7 on page
Table 7 on
126). If the VD[3]
Table 7
129