TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 216
![IC PCI-VME BRIDGE 456PBGA](/photos/6/93/69324/tsi148-133il_sml.jpg)
TSI148-133IL
Manufacturer Part Number
TSI148-133IL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133IL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
800-1905
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10. Registers > Register Map
216
P66M (PCI 66 MHz): This bit indicates the Tsi148 is capable of supporting a 66.67 MHz
PCI/X bus.
CAPL (Capabilities List): This bit indicates that the address at offset 0x34 is a pointer for a
New Capabilities linked list.
SERR (System Error Enable): This bit enables the SERR_ output pin. If cleared, the Tsi148
never drives SERR_. If set, the Tsi148 drives SERR_ active when a system error is detected.
PERR (Parity Error Response): This bit enables the PERR_ output pin. If cleared, the
Tsi148 never drives PERR_. If set, the Tsi148 drives PERR_ active when a data parity error is
detected.
MSTR (Bus Master Enable): If set, the Tsi148 may act as a master on PCI/X. If cleared, the
Tsi148 may not act as a master.
MEMSP (Memory Space Enable): If set, the Tsi148 does respond to PCI/X memory space
accesses when appropriate. If cleared, the Tsi148 does not respond to PCI/X memory space
accesses.
IOSP (I/O Space Enable): This bit is hard wired to zero. The Tsi148 does not respond to
PCI/X I/O space accesses.
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
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