TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 218

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

10. Registers > Register Map
10.4.10
Table 43: Cache Line Size / Master Latency Timer / Header Type Register
Cache Line Size / Master Latency Timer / Header Type Register
218
Register Name: HEAD/MLAT/CLSZ
PCI Reset Value: 0x
PCI-X Reset Value: 0x
31:24
23:16
15:08
31:24
23:16
Bits
15:8
Bits
7:0
7:0
Reserved
HEAD
MLAT
Name
CLSZ
Cache Line Size / Master Latency Timer / Header Type Registers
CLSZ (Cache Line): These bits represent the number of 32-bit words that define a
cache-line. A cache line is defined as 32-bytes, which is eight 32-bit words. If a value of 0x08
is written to this register, the value is retained. If any other value is written to this register, a
value of 0x00 is retained.
The PCI Local Bus Specification (Revision 2.2) states that this register must power up to all
zeros. The Tsi148 does not generate memory write and invalidate command. This register is
only used to inform other PCI/X masters of the supported cache-line size for read, read line,
and read multiple commands.
MLAT (Master Latency Timer): These bits represent the value used for the Master Latency
Timer. The Master Latency Timer specifies the amount of PCI/X clock periods that Tsi148
can remain on the PCI/X bus during burst cycles after GNT_ is taken away. The MLAT bits
provides a minimum granularity of the 8 PCI/X clock periods.
7
N/A
Header Type
Master Latency Timer
Cache Line Size
6
5
Function
4
Reserved
HEAD
MLAT
CLSZ
3
Register Offset: PCFS + 0x0C - CRG + 0x00C
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Type
R/W
R/W
R
R
2
Reset
P/S/L
P/S/L
N/A
N/A
By
1
80A3020_MA001_13
Value
Reset
0x00
0x00
0x00
0x00
PCI
PCI-X
Reset
Value
0x00
0x00
0x40
0x00
0