DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 8

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
(V
SFP+ Controller with Digital LDD Interface
NONVOLATILE MEMORY CHARACTERISTICS
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Note 11: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
Note 12: I
Note 13: C
Note 14: EEPROM write begins after a STOP condition occurs.
8
2
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP and START
Condition
START Hold Time
START Setup Time
Data In Hold Time
Data In Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
STOP Setup Time
Capacitive Load for Each Bus Line
EEPROM Write Time
EEPROM Write Cycles
CC
CC
C AC ELECTRICAL CHARACTERISTICS
_______________________________________________________________________________________
= +2.85V to +5.5V, T
= +2.85V to +5.5V, unless otherwise noted.)
PARAMETER
All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Inputs are at supply rail. Outputs are not loaded.
Eight ranges allow the full-scale range to change from 312mV to 1.25V.
The output impedance of the device is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance is 1.5kΩ.
This parameter is guaranteed by design.
Full-scale is programmable.
A temperature conversion is completed and the MODULATION register value is recalled from the LUT and V
measured to be above the VCC LO alarm.
The timing is determined by the choice of the SAMPLE RATE setting (see Table 02h, Register 88h).
This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
steps, the bias current will be within 3% within the time specified by the binary search time. See the BIAS and MODULA-
TION Control During Power-Up section.
dard-mode timing.
2
C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I
B
—the total capacitance of one bus line in pF.
PARAMETER
A
= -40°C to +95°C, timing referenced to V
SYMBOL
SYMBOL
t
t
t
t
t
HD:STA
HD:DAT
SU:DAT
SU:STO
SU:STA
t
t
f
HIGH
t
LOW
t
SCL
BUF
C
At +25°C
At +85°C
WR
t
t
R
F
B
(Note 12)
(Note 13)
(Note 13)
(Note 14)
CONDITIONS
CONDITIONS
IL(MAX)
and V
IH(MIN)
, unless otherwise noted.) (Figure 19)
20 + 0.1C
20 + 0.1C
200,000
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
50,000
MIN
0
0
B
B
TYP
TYP
MAX
MAX
400
300
300
400
0.9
20
CC
2
C stan-
has been
UNITS
UNITS
kHz
ms
pF
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs