DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 31
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
DS1878T+T&R
Manufacturer Part Number
DS1878T+T&R
Description
IC CTLR SFP W/DGTL LDD RX 28TQFN
Manufacturer
Maxim Integrated Products
Type
SFP+ Controllerr
Datasheet
1.DS1878TTR.pdf
(98 pages)
Specifications of DS1878T+T&R
Input Type
*
Output Type
*
Interface
*
Current - Supply
*
Mounting Type
Surface Mount
Package / Case
28-WFQFN exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (2Mb)
The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is locat-
ed in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two
memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For more
information about each of these bytes see the corresponding register description.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
(HEX)
30–5F
Read
Access
Write
Access
ROW
ACCESS
00
08
10
18
20
28
60
68
70
78
CODE
<1>
<1>
<1>
<1>
<1>
<1>
ROW NAME
<1>
<2>
<0>
THRESHOLD
THRESHOLD
THRESHOLD
THRESHOLD
THRESHOLD
THRESHOLD
VALUES
VALUES
<2>
<0>
SELECT
separately
WARN
See each
EEPROM
ALARM/
bit/byte
SFP+ Controller with Digital LDD Interface
TABLE
ADC
ADC
<0>
0
1
______________________________________________________________________________________
0
1
2
3
4
5
PW2
<1>
BYTE 0/8
All
ALARM
MON1 ALARM HI
MON2 ALARM HI
MON3 ALARM HI
MON4 ALARM HI
<2>
TEMP ALARM HI
EE
V
<2>
TEMP VALUE
CC
MON3 VALUE
WORD 0
RESERVED
3
ALARM HI
<2>
N/A
All
BYTE 1/9
ALARM
hardware
EE
All and
device
<3>
All
2
RESERVED
BYTE 2/A
ALARM
PW2 +
mode
LOWER MEMORY
MON1 ALARM LO
MON2 ALARM LO
MON3 ALARM LO
MON4 ALARM LO
PW2
TEMP ALARM LO
<4>
<2>
<2>
bit
V
EE
CC
V
MON4 VALUE
WORD 1
CC
ALARM LO
1
VALUE
<5>
All
All
BYTE 3/B
ALARM
EE
<6>
PWE MSW
0
<6>
N/A
All
BYTE 4/C
WARN
MON1 WARN HI
MON2 WARN HI
MON3 WARN HI
MON4 WARN HI
TEMP WARN HI
EE
<2>
MON1 VALUE
V
PW1
PW1
<7>
CC
WORD 2
3
RESERVED
Lower Memory Register Map
WARN HI
Register Descriptions
BYTE 5/D
WARN
PW2
PW2
<8>
EE
<6>
2
PWE LSW
PW2
<9>
N/A
<0>
BYTE 6/E
STATUS
MON1 WARN LO
MON2 WARN LO
MON3 WARN LO
MON4 WARN LO
TEMP WARN LO
EE
V
MON2 VALUE
CC
RESERVED
WORD 3
<10>
PW2
N/A
WARN LO
<3>
BYTE 7/F
<5>
UPDATE
SEL
EE
<11>
PW1
TBL
All
31
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