DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 21

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In LUT mode, DAC1 and DAC2 are each controlled by
a separate 8-bit, 4°C-resolution, temperature-
addressed LUT. The delta-sigma outputs use a 10-bit
structure. The 8-bit LUTs are either loaded directly into
the MSBs (8:1) or the LSBs (7:0). This is determined by
DAC1TI (Table 02h, Register C3h), DAC2TI (Table 02h,
Register C4h), DAC1TC (Table 02h, Register C6h, bit
6), and DAC2TC (Table 02h, Register C6h, bit 5). See
Figure 13 for more details. The DAC1 LUT (Table 07h)
and DAC2 LUT (Table 08h) registers are nonvolatile
and password-2 protected.
The reference input, REFIN, is the supply voltage for
the output buffer of DAC1 and DAC2. The voltage con-
nected to REFIN must be able to support the edge rate
requirements of the delta-sigma outputs. In a typical
application, a 0.1µF capacitor should be connected
between REFIN and ground.
Five digital input and four digital output pins are provid-
ed for monitoring and control.
By default (LOSC = 1, Table 02h, Register 89h), the
LOS pin is used to convert a standard comparator out-
put for loss of signal (LOS) to an open-collector output.
This means the mux shown in the Block Diagram by
default selects the LOS pin as the source for the
LOSOUT output transistor. The output of the mux can
be read in the STATUS byte (Lower Memory,
Register 6Eh) as the RXL bit. The RXL signal can be
inverted (INV LOS = 1) before driving the open-drain
output transistor using the XOR gate provided. Setting
Figure 13. DAC1/DAC2 LUT Assignments
SFP+ Controller with Digital LDD Interface
8
7
6
5
4
3
2
1
0
-40
______________________________________________________________________________________
LUT LOADED TO [7:0]
DAC[1/2]TC = 0
DAC[1/2]TI
TEMPERATURE (°C)
Digital I/O Pins
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
LOS, LOSOUT
+102
LOSC = 0 configures the mux to be controlled by LOS
LO, which is driven by the output of the LOS quick trip
(Table 02h, Registers BEh and BFh). The mux setting
(stored in EEPROM) does not take effect until V
POA, allowing the EEPROM to recall.
The digital input IN1 and RSEL pins primarily serve to
meet the rate-select requirements of SFP and SFP+.
They also serve as general-purpose inputs. RSELOUT
is driven by a combination of the RSEL and logic dictat-
ed by control registers in the EEPROM (Figure 15). The
levels of IN1 and RSEL can be read using the STATUS
register (Lower Memory, Register 6Eh). The open-drain
RSELOUT output is software-controlled and/or inverted
through the STATUS register and CNFGA register
(Table 02h, Register 89h). External pullup resistors
must be provided on RSELOUT to realize a high logic
level. The RSEL pin determines the value sent by the
3-wire master to the limiting amplifier’s SETLOS regis-
ter. When RSEL is high, SETLOSH is used. When RSEL
is low, SETLOSL is used.
TXDOUT is generated from a combination of TXFOUT,
TXD, and the internal signal FETG. A software control
identical to TXD is available (TXDC, Lower Memory,
Register 6Eh). A TXD pulse is internally extended
(t
ings related to the APC loop to allow for the loop to sta-
bilize. The nonlatching alarms and warnings are TXP
LO, LOS LO, and MON1–MON4 LO alarms and warn-
ings. In addition, TXP LO is disabled from creating
INITR1
8
7
6
5
4
3
2
1
0
-40
) to inhibit the latching of low alarms and warn-
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
DAC[1/2]TI
TEMPERATURE (°C)
LUT LOADED TO [7:0]
DAC[1/2]TC = 1
IN1, RSEL, RSELOUT
TXD, TXDOUT
+102
CC
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