DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 15

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

temperature, so the t
to recall the APC and MOD set points from EEPROM.
If TXD is asserted (logic 1) during normal operation,
the 3-wire master writes the laser driver bias and
MODULATION DACs to 0. When TXD is deasserted
(logic 0), the device sets the MODULATION register
with the value associated with the present temperature,
and initializes the BIAS register using the same search
algorithm as done at startup. When asserted, soft TXD
(TXDC) (Lower Memory, Register 6Eh) would allow a
software control identical to the TXD pin (see Figure 3).
As shown in Figure 4, the device’s input comparator is
shared between the APC control loop and the quick-
trip alarms (TXP HI, TXP LO, LOS, BIAS HI, and IBIAS
MAX). The comparator polls the alarms in a multiplexed
sequence. Five of every eight comparator readings are
used for APC loop bias-current control. The other three
updates are used to check the HTXP/LTXP (monitor
diode voltage), the HBATH (MON1), and LOS (MON3)
signals against the internal APC, BIAS, and MON3 ref-
erence, respectively. If the last APC comparison was
higher than the APC set point, it makes an HTXP com-
parison, and if it is lower, it makes an LTXP compari-
son. Depending on the results of the comparison, the
corresponding alarms and warnings (TXP HI, TXP LO)
are asserted or deasserted.
Figure 3. TXD Timing
Figure 4. APC Loop and Quick-Trip Sample Timing
BIAS and MODULATION Registers as a
APC QUICK-TRIP SAMPLE TIMES
Function of Transmit Disable (TXD)
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________
INIT
APC and Quick-Trip Timing
time is not required for the device
SAMPLE
HBIAS
TXDOUT
TXD
SAMPLE
APC
t
REP
SAMPLE
APC
t
OFF
SAMPLE
APC
The device has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options and time
delays resulting from writing values to the laser driver’s
bias DAC. The SAMPLE RATE register (Table 02h,
Register 88h) determines the sampling time. Samples
occur at a regular interval, t
sample rate options available. Any quick-trip alarm that
is detected by default remains active until a subse-
quent comparator sample shows the condition no
longer exists. A second bias current monitor (BIAS
MAX) compares a Maxim laser driver’s BIAS DAC’s
code to a digital value stored in the IBIASMAX register.
This comparison is made at every bias current update
to ensure that a high-bias current is quickly detected.
Table 2. Update Rate Timing
t
SAMPLE
ON
APC
APC_SR[2:0]
SAMPLE
APC
000b
001b
010b
011b
100b
101b
110b
111b
HTXP/LTXP
SAMPLE
SAMPLE
LOS
REP
SAMPLE PERIOD (t REP )
. Table 2 shows the
SAMPLE
HBIAS
1200
1600
2000
2800
3200
4400
6400
(ns)
800
SAMPLE
APC
15