DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 19

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The device contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the
supply voltage rises above POA, the outputs are dis-
abled, all SRAM locations are set to their defaults,
shadowed EEPROM (SEE) locations are zero, and all
analog circuitry is disabled. When V
the SEE is recalled, and the analog circuitry is enabled.
While V
mal operating state, and it responds based on its non-
volatile configuration. If during operation V
below POA, but is still above POD, then the SRAM
retains the SEE settings from the first SEE recall, but the
Figure 9. RSSI with Crossover Disabled
Figure 10. Low-Voltage Hysteresis Example
V
SEE
CC
V
V
POA
POD
PRECHARGED
CC
TO 0
SEE RECALL
remains above POA, the device is in its nor-
SFP+ Controller with Digital LDD Interface
RSSI RESULT
______________________________________________________________________________________
RECALLED VALUE
FINE
Low-Voltage Operation
HYSTERESIS
CC
reaches POA,
PRECHARGED TO 0
CC
COARSE
SEE RECALL
falls
device analog is shut down and the outputs disabled. If
the supply voltage recovers back above POA, then the
device immediately resumes normal operation. If the
supply voltage falls below POD, then the device SRAM
is placed in its default state and another SEE recall is
required to reload the nonvolatile settings. The
EEPROM recall occurs the next time V
POA. Figure 10 shows the sequence of events as the
voltage varies.
Any time V
used to determine if V
accomplished by checking the RDYB bit in the STATUS
(Lower Memory, Register 6Eh) byte. RDYB is set when
V
CC
is below POA; when V
CC
is above POD, the I
RECALLED VALUE
CC
is below the POA level. This is
CC
MON3 INPUT
rises above POA, RDYB
2
C interface can be
CC
PRECHARGED
exceeds
TO 0
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